[AK4679]
CONT6: Signal Setting 2
Register Name
CONT6
D7
0
D6
0
D5
D4
0
D3
0
D2
D1
0
D0
0
Register
Address
DSPRSTN
DLRDY
W
C6h
R
46h
R/W
Default
R
0
R
0
R/W
0
R
0
R
0
R/W
0
R
0
R
0
DLRDY: DSP Download Preparation
0: download inhibit (default)
1: download ready
This bit is used when start to download the DSP programs. The bit must be cleared after downloading
programs are completed.
DSPRSTN: DSP Reset
0: DSP Reset (default)
1: DSP Reset Release
CONT7: State Signal (Read only)
Register
Address
Register Name
CONT7
R/W
D7
SYDET
D6
CGLK
R
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
0
R
0
W
R
R
0
C7h
47h
Default
0
DSP status output from the wait sync state to operational state (Run State)
SYDET: SYNC Signal Detection flag
0: No SYNC1 pin Signal (Low or High fixed) (default)
1: SYNC1 pin Signal Detect
This bit outputs DSP status in Wait Sync State until DSP Operational state (RUN).
CGLK: Clock Generator Unit Lock Status
0: Clock Generator Unlocked State (default)
1: Clock Generator Locked State
CONT8: Initial Setting 4
Register
Address
Register Name
CONT8
R/W
D7
TESTC
R/W
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
0
R
0
D1
0
R
0
D0
0
R
0
W
R
C8h
48h
Default
TESTC bit must be set “1”. (i.e. set the 80h value in this register)
The TESTC bit is set after writing the power control register with the power suplly on.
MS1402-E-06
2013/02
- 190 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
