[AK4679]
SYNC1, 2, 3
BCLK1, 2, 3
SDOUTx
0
1
2
10 11 12 13 14 15
n-1
n
0
1
2
11 10 12 13 14 15
n-1
n
0
1
0
0
15 14
15 14
5
5
4
4
3
3
2
1
15 14
15 14
5
5
4
4
3
3
2
2
1
1
0
0
15
2
1
Don’t Care
Don’t Care 15
SDINx
15: MSB, 0: LSB
(x = 1 to 4)
Lch Data
Rch Data
Figure 114. Left Justified format (LAW bits = “00”, DIFD bits = “10”)
SYNC1, 2, 3
0
1
2
18 19
20
21 22 23
n-1
n
0
1
2
18
19 20 21
22
23
n-1
n
0
1
BCLK1, 2, 3
SDOUTx
23 22
23 22
5
5
4
4
3
3
2
1
1
0
0
23 22
5
5
4
4
3
3
2
2
1
1
0
23
2
Don’t Care 23 22
0
Don’t Care 23
SDINx
23:MSB, 0:LSB
(x = 1 to 4)
Lch Data
Rch Data
Figure 115. Left Justified format (LAW bits = “01”, DIFD bits = “10”)
SYNC1, 2, 3
0
1
2
3
11
12
13
14
15 16
n
0
1
2
3
11
12
13 14
15
16
n
0
1
BCLK1, 2, 3
SDOUTx
15 14
15 14
5
5
4
4
0
0
15 14
15 14
5
5
4
4
3
3
2
1
1
3
3
2
2
1
1
0
0
2
Don’t Care
Don’t Care
SDINx
15:MSB, 0:LSB
Lch Data
Rch Data
(x=1 to 4)
Figure 116. I2S Format (LAW bits = “00”, DIFD bits = “11”)
SYNC1, 2, 3
0
1
2
3
19
20
21
22
23 24
n
0
1
2
3
19
20
21 22
23
24
n
0
1
BCLK1, 2, 3
SDOUTx
23 22
23 22
5
5
4
4
23 22
23 22
5
5
4
4
3
3
2
1
1
0
0
3
3
2
2
1
1
0
0
2
Don’t Care
Don’t Care
SDINx
23:MSB, 0:LSB
Lch Data
Rch Data
(x=1 to 5)
Figure 117. I2S Format (LAW bits = “01”, DIFD bits = “11”)
MS1402-E-06
2013/02
- 139 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
