[AK4679]
■ Power-up Sequence and Device Setting
• Power-up, register setting, program download and RUN state sequence
The DSP must be in sleep state when downloading the program. Set DLRDY bit to “1” to power-up the internal
oscillation circuit, and after 100μs downloading becomes available. DLRDY bit must always be cleared when complete a
download. Then DSPTRSTN bit is cleared, the DSP block enters wait sync mode. In this state, CGU block is locked when
serial data clock input is detected and the DSP block becomes operating state.
Power supply
0.6μs (min)
PDNE(pin)
1μs (min)
PWSW bit
MRSTN bit
μP I/F
Setting Register
Download DSP program
100 μs(min)
DLRDY bit
100 μs(min)
Glock Gen(int.)
DSPRSTN bit
BCLKx,SYNCx pin
(x= 1 or 3)
Don’t care
Input
Device state
Sleep State
Wait Sync
Device Operational State
Power OFF
Power Down
Hardware Reset→Suspend
Figure 119. DSP Block Status
MS1402-E-06
2013/02
- 143 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
