[AK4679]
■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins in full-differential as (L+R) signal.
The load impedance is 10kΩ (min) for each LOP pin and LON pin. When the PMLO = PMRO bits = “0”, the mono line
output enters power-down mode and the output is pulled-down to VSS1. When the PMLO = PMRO bits = “1” and LOPS
bit = “1”, mono line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO and
PMRO bits when LOPS bit = “1”. When PMLO = PMRO bits = “1” and LOPS bit = “0”, mono line output enters in
normal operation. LVL2-0 bits set the volume of mono line output.
LVL2-0 bits
DACL bit
DAC Lch
DAC Rch
LOP pin
LON pin
M
I
X
DACR bit
Figure 80. Full-differential Mono Line Output
LVL2-0 bits
Attenuation
N/A
7H
6H
5H
4H
3H
2H
1H
0H
N/A
+12dB
+9dB
+6dB
+3dB
0dB
(default)
−3dB
Table 102. Mono Line Output Gain Setting (N/A: Not available)
LOPS bit
0
PMLO/RO bits
Mode
Power-down
Normal Operation
Power-save
LON/LOP pins
Pull-down to VSS1
Normal Operation
Fall down to VSS1
0
1
0
1
(default)
1
Power-save
Rise up to common voltage
Table 103. Mono Line Output Mode Setting
MS1402-E-06
2013/02
- 112 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
