[AK4646]
■ Stop of Clock
Master clock can be stopped when ADC and DAC are not used.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"0" or "1"
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
(Addr:01H, D1)
(3)
External MCKI
Input
Figure 46. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
(1)
PMPLL bit
(Addr:01H, D0)
BICK frequency: 64fs
(2)
External BICK
External LRCK
Input
Input
(1) Addr:01H, Data:00H
(2)
(2) Stop the external clocks
Figure 47. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
MS0557-E-05
2011/01
- 75 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
