[AK4646]
3. PLL Slave (MCKI pin)
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
(1)
PMPLL bit
(Addr:01H, D0)
BICK frequency: 64fs
(1)
MCKO bit
(Addr:01H, D1)
(1) Addr:01H, Data:00H
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 48. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
4. EXT Slave Mode
(1)
External MCKI
Input
Example
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
(1)
(1)
External BICK
External LRCK
Input
Input
(1) Stop the external clocks
Figure 49. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
■ Power down
Power supply current can be shut down (typ. 1μA) by stopping clocks and setting PMVCM bit = “0” after all blocks
except for VCOM are powered-down. Power supply current can be also shut down (typ. 1μA) by stopping clocks and
setting PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
MS0557-E-05
2011/01
- 76 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
