[AK4646]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock for the
AK4646 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 5).
12MHz, 13.5MHz, 24MHz, 27MHz
AK4646
DSP or μP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
≥ 32fs
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
Figure 13. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0557-E-05
2011/01
- 23 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
