[AK4646]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (12MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK
clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (Table 9) and the
output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (Table 10).
12MHz, 13.5MHz, 24MHz, 27MHz
AK4646
DSP or μP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
32fs, 64fs
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
Figure 12. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
1
2
3
0
0
1
1
0
1
0
1
256fs
128fs
64fs
(default)
32fs
Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BICK Output
BCKO bit
Frequency
0
1
32fs
64fs
(default)
Table 10. BICK Output Frequency at Master Mode
MS0557-E-05
2011/01
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
