[AK4646]
b) PLL reference clock: BICK or LRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4646
MCKO
DSP or μP
MCKI
32fs or 64fs
BCLK
LRCK
BICK
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
Figure 14. PLL Slave Mode 2 (PLL Reference Clock: LRCK or BICK pin)
AK4646
MCKO
DSP or μP
MCKI
≥ 32fs
BCLK
LRCK
BICK
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
Figure 15 PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4646 may draw
excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external
clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”).
MS0557-E-05
2011/01
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
