[AK4646]
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4646 is supplied stable clocks after PLL is
powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency is changed.
1) Setting of PLL Mode
PLL
Reference
Clock Input
Pin
R and C of
VCOC pin
PLL Lock
Time
(max)
PLL3 PLL2 PLL1 PLL0
Input
Frequency
Mode
bit
bit
bit
bit
C[F]
R[Ω]
0
1
2
0
0
0
0
0
0
0
0
1
0
1
0
LRCK pin
N/A
BICK pin
1fs
-
32fs
6.8k
-
220n
-
160ms
-
2ms
4ms
2ms
(default)
10k
10k
10k
10k
10k
10k
10k
10k
4.7n
10n
4.7n
10n
10n
10n
10n
10n
3
0
0
1
1
BICK pin
64fs
4ms
6
7
12
13
Others
0
0
1
1
1
1
1
1
1
0
0
0
1
0
1
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
12MHz
24MHz
13.5MHz
27MHz
40ms
40ms
40ms
40ms
1
Others
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
Mode
0
1
2
3
4
5
6
7
10
11
14
15
Others
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
8kHz
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
(default)
12kHz
16kHz
24kHz
7.35kHz
11.025kHz
14.7kHz
22.05kHz
32kHz
48kHz
29.4kHz
44.1kHz
N/A
Others
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin)
When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and
FS2 bits. (Table 6).
FS3 bit
FS2 bit
Sampling Frequency
Range
Mode
FS1 bit
FS0 bit
0
0
1
0
1
0
Don’t care
Don’t care
Don’t care
0
1
2
Don’t care
Don’t care
Don’t care
(default)
7.35kHz ≤ fs ≤ 12kHz
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
N/A
Others
Others
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference: Clock: LRCK or BICK pin)
MS0557-E-05
2011/01
- 20 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
