[AK4646]
1/fCLK
VIH
VIL
MCKI
LRCK
tCLKH
tCLKL
1/fs
VIH
VIL
tLRCKH
tBCK
tLRCKL
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
VIL
BICK
tBCKH
tBCKL
tMCKL
fMCK
50%DVDD
MCKO
dMCK = tMCKL x fMCK x 100
Figure 4. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
BICK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tLRCKH
tBCK
tLRCKL
VIH
VIL
tBCKH
tBCKL
Figure 5. Clock Timing (EXT Slave mode)
MS0557-E-05
2011/01
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