[AK4646]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing
Master Mode
tMBLR
tLRD
-
-
40
70
ns
ns
BICK “↓” to LRCK Edge (Note 27)
LRCK Edge to SDTO (MSB)
(Except I2S mode)
−40
−70
tBSD
tSDH
tSDS
-
-
-
70
-
-
ns
ns
ns
BICK “↓” to SDTO
−70
50
50
SDTI Hold Time
SDTI Setup Time
Slave Mode
tLRB
tBLR
tLRD
50
50
-
-
-
-
-
-
80
ns
ns
ns
LRCK Edge to BICK “↑” (Note 27)
BICK “↑” to LRCK Edge (Note 27)
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
tSDH
tSDS
-
50
50
-
-
-
80
-
-
ns
ns
ns
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse Width High
-
CDTIO Setup Time
CDTIO Hold Time
-
-
CSN “H” Time
-
-
-
70
70
CSN Edge to CCLK “↑” (Note 28)
CCLK “↑” to CSN Edge (Note 28)
CCLK “↓” to CDTIO (at Read Command)
CSN “↑” to CDTIO (Hi-Z) (at Read Command)
Power-down & Reset Timing
tCSH
tDCD
tCCZ
-
PDN Pulse Width
PMADL or PMADR “↑“ to SDTO valid
(Note 29)
(Note 30)
tPD
tPDV
150
-
-
-
-
ns
1/fs
1059
Note 27. BICK rising edge must not occur at the same time as LRCK edge.
Note 28. CCLK rising edge must not occur at the same time as CSN edge.
Note 29. The AK4646 can be reset by the PDN pin = “L”.
Note 30. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
MS0557-E-05
2011/01
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
