[AK4646]
■ Timing Diagram
1/fCLK
VIH
VIL
MCKI
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
1/fMCK
MCKO
50%DVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Note 31. MCKO is not available at EXT Master mode.
Figure 2. Clock Timing (PLL / EXT Master mode)
50%DVDD
LRCK
tBLR
tBCKL
BICK
SDTO
SDTI
50%DVDD
50%DVDD
tDLR
tBSD
tSDS
tSDH
VIH
VIL
Figure 3. Audio Interface Timing (PLL/EXT Master mode)
MS0557-E-05
2011/01
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