[AK4634]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or FCK pin. The required clock to the
AK4634 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency
is 16fs, the audio interface format supports Mode 0 only (DSP Mode).
a) PLL reference clock: MCKI pin
BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK is not important.
The MCKO pin outputs the frequency selected by FS3-0 bits (Table 5)
12MHz, 13.5MHz,
24MHz, 27MHz
AK4634
DSP or μP
MCKI
256fs
MCLK
BCLK
FCK
MCKO
BICK
FCK
16fs, 32fs, 64fs
1fs
SDTI
SDTO
SDTI
SDTO
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0983-E-00
2008/07
- 27 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
