[AK4634]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the MCKO, BICK and FCK
clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs, the output is enabled by
MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits. (Table 9)
In DSP mode, FCK output can select Duty 50% or High-output only during 1 BICK cycle (Table 10). Except DSP mode,
FCKO bit should be set “0”.
When BICK output frequency is 16fs, the audio interface format supports Mode 0 only (DSP Mode).
12MHz, 13.5MHz,
24MHz, 27MHz
AK4634
DSP or μP
MCKI
256fs
MCLK
BCLK
FCK
MCKO
BICK
FCK
16fs, 32fs, 64fs
1fs
SDTI
SDTO
SDTI
SDTO
Figure 19. PLL Master Mode
BICK Output
Frequency
Mode
BCKO1
BCKO0
0
1
2
3
0
0
1
1
0
1
0
1
16fs
32fs
64fs
N/A
(default)
Table 9. BICK Output Frequency at Master Mode
Mode
0
1
FCKO
FCK Output
Duty = 50%
High Width = 1/fBCK
0
1
(default)
fBCK is BICK Output Frequency.
Table 10. FCK Output at PLL Master Mode and DSP Mode
MS0983-E-00
2008/07
- 26 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
