[AK4634]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4634 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits (Table 14). The BICK is selected among 32fs or 64fs, by BCKO1-0
bits (Table 15). FCK bit should be set to “0”.
Mode
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Frequency
256fs
Sampling Frequency
Range
x
x
x
x
0
1
0
1
(default)
0
1
2
3
0
0
1
1
7.35kHz ≤ fs ≤ 48kHz
7.35kHz ≤ fs ≤ 13kHz
7.35kHz ≤ fs ≤ 26kHz
7.35kHz ≤ fs ≤ 48kHz
1024fs
512fs
256fs
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care)
External Master Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.
MCKI should always be present whenever the ADC, DAC, SPK or Programmable Filter is in operation (PMADC =
PMDAC = PMSPK bit = PMPFIL bits = “1”). If MCKI is not provided, the AK4634 may draw excess current and it is not
possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC, DAC,
SPK and Programmable Filter should be in the power-down mode (PMADC = PMDAC = PMSPK = PMPFIL bits = “0”).
AK4634
MCKO
DSP or μP
256fs, 512fs or 1024fs
MCKI
BICK
FCK
MCLK
BCLK
FCK
32fs, 64fs
1fs
SDTI
SDTO
SDTI
SDTO
Figure 24. EXT Master Mode
BICK Output
Frequency
Mode
BCKO1
BCKO0
0
1
2
3
0
0
1
1
0
1
0
1
N/A
32fs
64fs
N/A
(default)
Table 15. BICK Output Frequency at Master Mode (N/A: Not available)
MS0983-E-00
2008/07
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AKM [ ASAHI KASEI MICROSYSTEMS ]
