[AK4634]
When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2
bits. (Table 6)
FS3 bit
FS2 bit
Sampling Frequency
Range
Mode
FS1 bit
FS0 bit
0
0
1
0
1
0
x
x
x
0
1
2
x
x
x
(default)
7.35kHz ≤ fs ≤ 12kHz
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
N/A
Others
Others
(x: Don’t care, N/A: Not available)
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”
■ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, irregular frequency clocks are output from FCK, BICK and MCKO pins after PMPLL bit = “0” Æ “1” or
sampling frequency is changed. After that PLL is unlocked, the BICK and FCK pins output “L” for a moment, and invalid
frequency clock is output from the MCKO pin at MCKO bit = “1”. If the MCKO bit is “0”, the MCKO pin is output to
“L”.
(Table 7)
When sampling frequency is changed, BICK and FCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
MCKO bit = “0” MCKO bit = “1”
PLL State
BICK pin
FCK pin
After that PMPLL bit “0” Æ “1”
PLL Unlock
PLL Lock
“L” Output
“L” Output
“L” Output
Invalid
Invalid
256fs Output
“L” Output
Invalid
See Table 9
“L” Output
Invalid
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is
changed. After that, 256fs is output from the MCKO pin when PLL is locked. ADC and DAC output invalid data when
the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACA and DACS bits in Addr=02H.
MCKO pin
PLL State
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
PLL Unlock
PLL Lock
“L” Output
“L” Output
“L” Output
Invalid
Invalid
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MS0983-E-00
2008/07
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AKM [ ASAHI KASEI MICROSYSTEMS ]
