[AK4634]
■ Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4634 is power-down mode (PDN pin = “L”) and exits reset state, the AK4634 is slave mode. After exiting reset state,
the AK4634 changes to master mode by bringing M/S bit = “1”.
When the AK4634 is in master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. The FCK and
BICK pins of the AK4634 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating
state.
M/S bit
Mode
0
1
Slave Mode
Master Mode
(default)
Table 3. Select Master/Salve Mod
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4. Ether when the AK4634 is supplied to a stable clocks
after PLL is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency changes, the PLL lock time is the
same.
1) Setting of PLL Mode
R and C of
PLL Lock
VCOC pin
(Note 29)
PLL3 PLL2 PLL1 PLL0 PLL Reference
Input
Frequency
Mode
Time
bit
bit
bit
bit
Clock Input Pin
(max)
C[F]
R[Ω]
0
1
2
3
6
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
FCK pin
BICK pin
BICK pin
BICK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
1fs
16fs
32fs
6.8k
10k
10k
10k
10k
10k
10k
10k
220n
4.7n
4.7n
4.7n
4.7n
4.7n
10n
160ms
2ms
2ms
(default)
64fs
2ms
12MHz
24MHz
13.5MHz
27MHz
20ms
20ms
20ms
20ms
7
12
13
Others
1
10n
Others
Note 29. the tolerance of R is ±5%, the tolerance of C is ±30%
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
2) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is the MCKI pin), the sampling frequency is selected by FS2-0 bits as
defined in Table 5.
Mode
0
1
2
3
4
5
6
7
10
11
14
15
Others
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
8kHz
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
(default)
12kHz
16kHz
24kHz
7.35kHz
11.025kHz
14.7kHz
22.05kHz
32kHz
48kHz
29.4kHz
44.1kHz
N/A
Others
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (N/A: Not available)
MS0983-E-00
2008/07
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
