[AK4480]
■ Register Control Interface
Functions of the AK4480 can be controlled in parallel control mode (by pins) and serial control mode (by registers). In
parallel control mode, the register setting is ignored, and in serial control mode the pin settings are ignored. When the state
of the PSN pin is changed, the AK4480 should be reset by the PDN pin. The serial control interface is enabled by the PSN
pin = “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK and CDTI. The data on this
interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit; fixed to “1”), Register address (MSB first, 5-bits) and
Control data (MSB first, 8-bits). The AK4480 latches the data on the rising edge of CCLK, so data should be clocked in on
the falling edge. The writing of data is valid when CSN “↑”. The clock speed of CCLK is 5MHz (max).
Function
Parallel Control Mode Serial Control Mode
Audio Format
Auto Setting Mode
De-emphasis
SMUTE
DSD Mode
Y
-
Y
Y
-
-
-
Y
-
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EX DF I/F
Zero Detection
Sharp Roll Off Filter
Slow Roll Off Filter
Minimum delay Filter
Digital Attenuator
Table 20. Function List (Y: Available, -: Not available)
Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is
reset by the RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 16. Control I/F Timing
* The AK4480 does not support the read command.
* When the AK4480 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control
registers is prohibited.
* The control data can not be written when the CCLK rising edge is 15 times and less or 17 times and more during CSN is
“L”.
MS1146-E-03
2012/01
- 32 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
