[AK4480]
■ Reset Function
(1) RESET by RSTN bit = “0”
When RSTN bit = “0”, the AK4480’s digital section is powered down but the internal register values are not initialized.
The analog outputs become VCML/R voltage and DZF pins of both channels become “H”. Figure 14 shows the example
of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN Timing
Internal
State
Normal Operation
Digital Block
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(1)
(1)
(3)
(2)
(3)
D/A Out
(Analog)
(4)
Clock In
MCLK, BICK, LRCK
Don’t care
2/fs(5)
DZFL/DZFR
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) The analog outputs are VCOM voltage when RSTN bit = “0”.
(3) Click noise occurs at the edges (“↑ ↓”) of the internal timing of RSTN bit.
This noise is output even if “0” data is input.
(4) The DZF pins become “H” when the RSTN bit is set to “0”, and return to “L” in 2/fs after the RSTN bit is changed
to “1”.
(5) There is a delay, 3 ~ 4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2 ~ 3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) or Hi-z output (2) influences system applications. The timing
example is shown in this figure.
Figure 14. Reset Sequence Example 1
MS1146-E-03
2012/01
- 30 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
