[AK4480]
■ Power ON/OFF timing
The AK4480 is placed in power-down mode by bringing the PDN pin “L” and the registers are initialized. The analog
outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN signal, the analog output should be muted
externally if the click noise influences system application.
The AK4480 can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding
analog outputs become AVDD/2 (typ). As some click noise occurs at the edge of RSTN signal, the analog output should
be muted externally if the click noise influences system application.
Power
(1)
PDN pin
Internal
State
Normal Operation
Reset
DAC In
(Digital)
“0”data
“0”data
GD
(2)
GD
(3)
(4)
(4)
(3)
DAC Out
(Analog)
(5)
Don’t care
Clock In
MCLK,LRCK,BICK
Don’t care
(7)
DZFL/DZFR
External
Mute
(6)
Mute ON
Mute ON
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”). (DZFB bit = “0”)
Figure 13. Power-down/up Sequence Example
MS1146-E-03
2012/01
- 29 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
