[AK4480]
■ Register Map
Addr Register Name
00H Control 1
01H Control 2
02H Control 3
D7
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
D5
ECS
SD
DCKS
ATT5
ATT5
0
D4
0
DFS1
DCKB
ATT4
ATT4
0
D3
DIF2
DFS0
MONO
ATT3
ATT3
0
D2
DIF1
DEM1
DZFB
ATT2
ATT2
0
D1
DIF0
DEM0
SELLR
ATT1
ATT1
0
D0
RSTN
SMUTE
SLOW
ATT0
ATT0
0
ACKS
DZFE
DP
ATT7
ATT7
INVL
03H
04H
Lch ATT
Rch ATT
05H Control 4
Notes:
Data must not be written into addresses from 06H to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values.
When the state of the PSN pin is changed, the AK4480 should be reset by the PDN pin.
■ Register Definitions
Addr Register Name
00H Control 1
Default
D7
ACKS
0
D6
EXDF
0
D5
ECS
0
D4
0
0
D3
DIF2
0
D2
DIF1
1
D1
DIF0
0
D0
RSTN
1
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized.
1: Normal Operation (default)
When internal clocks are changed, the AK4480 should be reset by the PDN pin or RSTN bit.
DIF2-0: Audio Data Interface Modes (Table 14)
Initial value is “010” (Mode 2: 24-bit MSB justified).
ECS: Ex DF I/F mode clock setting (Table 15)
0: BCK 32fs setting. MCLK, BCK are 512fs, 256fs and 128fs (default)
1: No BCK 32fs setting. MCLK, BCK are 768fs, 384fs and 192fs.
EXDF: External Digital Filter I/F Mode (PCM only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
When ACKS bit is “1”, sampling frequency and MCLK frequency is detected automatically.
MS1146-E-03
2012/01
- 34 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
