[AK4480]
Addr Register Name
02H Control 3
Default
D7
DP
0
D6
0
0
D5
DCKS
0
D4
DCKB
0
D3
MONO
0
D2
DZFB
0
D1
SELLR
0
D0
SLOW
0
SLOW: Slow Roll-off Filter Enable
0: (default)
1: Slow roll-off filter
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output R channel data, when MONO mode. (default)
1: All channel output L channel data, when MONO mode.
In Mono mode, Rch’s date is output to both channels by setting SELLR bit = “0”, and Lch’s data is output
to both channels by setting SELLR bit = “1”. In Stereo mode, the output data of L and R channels are
switched their output ports by setting SELLR bit = “1”. (Table 19)
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
DZFB setting is valid regardless of the DZFE bit setting.
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP:
DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When D/P bit is changed, the AK4480 should be reset by RSTN bit.
Addr Register Name
03H Lch ATT
04H Rch ATT
Default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
ATT7-0: Attenuation Level
ATT = 20 log10 (ATT_DATA / 255) [dB]
FFH: 0dB (default)
00H: Mute
MS1146-E-03
2012/01
- 36 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
