[AK4438]
(3) Reset Function (MCLK)
The AK4438 is automatically placed in reset state when MCLK is stopped during normal operation (PDN
pin = “H”), and the analog outputs go to VCOM voltage. When MCLK are input again, the AK4438 exits
reset state and starts the operation. Zero detect function is disable when MCLK is stopped.
AVDD pin
TVDD pin
(1)
RSTN bit
Internal
State
Power-down
Power-down
Normal Operation
Digital Circuit Power-down
Normal Operation
D/A In
(Digital)
(4)
GD
GD
(2)
(2)
(3)
(5)
(5)
Hi-Z
D/A Out
(Analog)
(5)
(6)
Clock In
MCLK
MCLK Stop
External
MUTE
(6)
(6)
Notes:
(1) After AVDD and TVDD are powered-up, the PDN pin should be “L” for 800ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) When MCLK is stopped, analog outputs go to VCOM voltage.
(4) The digital data can be stopped. Click noise after MCLK is input again can be reduced by inputting
“0” data during this period.
(5) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK
inputs. This noise occurs even when “0” data is input.
(6) Mute the analog output externally if click noise (5) influences system applications. The timing
example is shown in this figure.
Figure 34. Reset Sequence Example2
016001925-E-00
2016/03
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AKM [ ASAHI KASEI MICROSYSTEMS ]
