[AK4438]
(2) Reset Function (RSTN bit)
The DAC can be reset by setting RSTN bit to “0” but the internal registers are not initialized. In this time,
the corresponding analog outputs go to VCOM and the DZF pin outputs “H” if clocks (MCLK, BICK and
LRCK) are input. Figure 33 shows an example of reset sequence by RSTN bit.
RSTN bit
(5)
3~4/fs
2~3/fs
Internal
RSTN bit
Internal
State
Normal Operation
Digital Block
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(1)
(1)
(3)
(2)
(3)
D/A Out
(Analog)
Clock In
BICK
Don’t care
(4)
2/fs
DZF
Notes:
(1) he analog output corresponding to digital input has group delay (GD).
(2) Analog outputs are VCOM in power down mode.
(3) Click noise occurs at the edges (“ ”) of the internal timing of RSTN bit. This noise is output even
if “0” data is input.
(4) The DZF pin goes to “H” on the falling edge of RSTN bit and goes to “L” in 2/fs after a rising edge
of the internal RSTN.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit
“1” to the internal RSTN bit “1”.
Figure 33. Reset Sequence Example
016001925-E-00
2016/03
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AKM [ ASAHI KASEI MICROSYSTEMS ]
