[AK4438]
■ Clock Synchronization
The AK4438 has a function that resets the internal counter to keep a falling edge of the internal FSI clock
is in 3/256fs from an edge of the external FSI clock. Clock synchronization function becomes valid when
data at all channels are continuously “0” for 8192 times if SYNCE bit is set to “1” during operation in PCM
mode or when RSTN bit is set to “0”. The operation clock is synchronized to a falling edge of LRCK in
PCM mode and a rising edge of LRCK in I2C mode.
The analog output becomes VCOM voltage when RSTN bit = “0” or zero data is detected. Figure 35
shows a synchronization sequence when the input data is “0” for 8192 times continuously. Figure 36
shows a synchronization sequence by RSTN bit.
(1) Clock Synchronization Sequence when Input Data is “0” for 8192 Cycles Continuously
The DZF pin goes to “H” and the synchronization function becomes enabled when input data is “0” for
8192 time continuously including when the data is attenuated. Figure 35 shows a synchronization
sequence.
D/A In
(Digital)
SMUTE
(1)
(1)
ATT_Level
Attenuation
-
GD
GD
GD
(4)
AOUT
(2)
8192/fs
(2)
8192/fs
DZF pin
Operation (2)
(5)
Operation (2)
Internal Counter
Reset
Internal
Data Reset
4~5/fs (3)
Notes:
(1) Refer to Table 14 internal transition time of ATT.
(2) The synchronization function becomes enabled when all channels input data are “0” for 8192 times
continuously.
(3) Internal data is fixed to “0” for 4~5/fs forcibly when the internal counter is reset.
(4) Click noise occurs when the internal counter is reset. This noise is output even if “0” data is input.
Mute the analog output externally if this click noise adversely affects system performance.
(5) The internal counter will not be reset when the internal and the external clocks are synchronized
even if the synchronization function is enabled.
Figure 35. Clock Synchronization Sequence with Continuous Zero Data
016001925-E-00
2016/03
- 45 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
