[AK4438]
■ Power Down Function
The AK4438 is placed in power-down mode by bringing the PDN pin “L” and the analog outputs become
floating (Hi-Z) state. Power-up and power-down timings are shown in Figure 31.
Power
(1)
PDN pin
LDOO pin
(2)
Internal PDN
Internal
State
Normal Operation (Register Write and DAC input are available)
Reset
DAC In
(Digital)
“0”data
“0”data
(3)
GD
GD
(4)
(5)
(5)
(4)
DAC Out
(Analog)
(6)
Don’t care
Clock In
MCLK,LRCK,BICK
Don’t care
(8)
DZF
External
Mute
(7)
Mute ON
Mute ON
Notes:
(1) After AVDD and TVDD are powered-up, the PDN pin should be “L” for 800ns.
(2) After PDN pin = “H”, the internal LDO and VCOM power-up. The internal registers are initialized.
Register writing is available in 1msec after PDN pin = “H”.
(3) The analog output corresponding to digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at an edge of PDN signal. This noise is output even if “0” data is input.
(6) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(7) Mute the analog output externally if click noise (5) adversely affect system performance
The timing example is shown in this figure.
(8) The DZF pin outputs “L” in internal power-down mode.
Figure 31. Pin Power Down/Up Sequence Example
016001925-E-00
2016/03
- 40 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
