[AK4438]
(1) Power OFF Function (PW4-1 bits)
All DAC4-1 can be powered down immediately by setting PW4-1 bits to “0000”. In this time, the analog
output goes to floating state (Hi-z). DACs will be reset and the digital block is powered down by setting
RSTN bit to “0”. In the reset state, the analog output becomes VCOM voltage if DAC is powered-up and
MCLK, LRCK and BICK are supplied (Table 20). Internal register values are not initialized by power-off or
reset by bit settings. Figure 32 shows a timing example of power-on and power-down.
PMDA4-1bit
Internal
State
Normal Operation
Power-off
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(1)
(1)
(3)
(6)
(2)
(3)
D/A Out
(Analog)
(4)
Clock In
MCLK, BICK, LRCK
Don’t care
DZF
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs are floating (Hi-Z) in power down mode.
(3) Click noise occurs at the edges (“ ”) of the internal timing of PW4-1 bits. This noise is output
even if “0” data is input.
(4) Each clock input (MCLK, BICK, LRCK) can be stopped in power down mode (PW4-1 bits =
“0000”).
(5) Mute the analog output externally if the click noise (3) adversely affect system performance.
(6) The DZF pin outputs “L”, in power down mode (PW4-1 bits = “0000”).
Figure 32. Power-off/on Sequence Example
016001925-E-00
2016/03
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AKM [ ASAHI KASEI MICROSYSTEMS ]
