[AK4438]
(2) Clock Synchronization Sequence with RSTN-bit
The DZF pin outputs “H” by setting RSTN bit to “0”. The DAC is reset after 3~4/fs from the DZF pin = “H”,
and the analog output goes to VCOM voltage. The synchronization function is enabled when the DZF pin
= “H”. Figure 36 shows synchronization sequence with RSTN bit.
RSTN bit
3~4/fs (4)
2~3/fs (4)
Internal
RSTN bit
Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
D/A In
(Digital)
force”0”
(2)
(3)
GD
GD
(3)
(5)
(5)
D/A Out
(Analog)
2/fs(4)
DZF
Operation (1)
Internal Counter
Reset
Internal
Data Reset
4~5/fs (2)
Notes:
(1) The DZF pin outputs “H” by a falling edge of RSTN bit, and returns to “L” after 2/fs from the internal
rising edge of RSTN bit. During this period the synchronization function is enabled.
(2) Internal data is fixed to “0” for 4~5/fs forcibly when the internal counter is reset.
(3) The analog output corresponding to digital input has group delay (GD). It is recommended that
when writing “0” data to RSTN bit, “0” period should be longer than the GD period.
(4) It takes 3~4/fs to fall down and 2~3/fs to rise up for the internal RSTN signal from RSTN bit writing.
There is a case that the internal counter is reset before internal RSTN bit is changed to “1” since the
synchronization function becomes enabled immediately by setting RSTN bit = “0”.
(5) A click noise occurs by an internal RSTN signal edge or an internal counter reset. This noise is
output even if “0” data is input. Mute the analog output externally if the click noise adversely affects
the system performance.
Figure 36. Clock Synchronization Sequence by RSTN bit
016001925-E-00
2016/03
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AKM [ ASAHI KASEI MICROSYSTEMS ]
