欢迎访问ic37.com |
会员登录 免费注册
发布采购

AK4372 参数 Datasheet PDF下载

AK4372图片预览
型号: AK4372
PDF下载: 下载PDF文件 查看货源
内容描述: DAC内置有PLL和HP- AMP [DAC with built-in PLL & HP-AMP]
分类和应用:
文件页数/大小: 62 页 / 1025 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
 浏览型号AK4372的Datasheet PDF文件第18页浏览型号AK4372的Datasheet PDF文件第19页浏览型号AK4372的Datasheet PDF文件第20页浏览型号AK4372的Datasheet PDF文件第21页浏览型号AK4372的Datasheet PDF文件第23页浏览型号AK4372的Datasheet PDF文件第24页浏览型号AK4372的Datasheet PDF文件第25页浏览型号AK4372的Datasheet PDF文件第26页  
[AK4372]  
EXT Mode (PMPLL bit = “0”: Default)  
The AK4372 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to “0”. In EXT mode, the  
master clock can directly input to the DAC via the MCKI pin without going through the PLL. In this case, the sampling  
frequency and MCKI frequency can be selected by FS3-0 bits (Table 11). In EXT mode, PLL4-0 bits are ignored. MCKO  
output is enabled by MCKO bit. The MCKO output frequency can be controlled by PS1-0 bits. If the sampling frequency  
is changed during normal operation of the DAC (PMDAC bit = “1”), the input must be muted by SMUTE bit = “1”, or set  
to “0” data.  
LRCK and BICK are output from the AK4372 in master mode(Figure 15). The clock input to the MCKI pin should  
always be present whenever the DAC is in normal operation (PMDAC bit = “1”). If these clocks are not provided, the  
AK4372 may draw excessive current and will not operate properly because it utilizes these clocks for internal dynamic  
refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit =  
“0”).  
AK4372  
MCKO  
DSP or μP  
256fs, 384fs, 512fs,  
768fs or 1024fs  
MCKI  
BICK  
LRCK  
MCLK  
BCLK  
LRCK  
32fs, 64fs  
1fs  
SDTO  
SDATA  
Figure 15. EXT Master Mode  
The external clocks required to operate the AK4372 in slave mode are MCKI, LRCK and BICK(Figure 16). The master  
clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter.  
All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode  
(PMDAC bit = “1”). If these clocks are not provided, the AK4372 may draw excessive current and will not operate  
properly, because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the  
DAC should be placed in power-down mode (PMDAC bit = “0”).  
AK4372  
MCKO  
DSP or μP  
256fs, 384fs, 512fs,  
768fs or 1024fs  
MCKI  
BICK  
LRCK  
MCLK  
BCLK  
LRCK  
32fs, 64fs  
1fs  
SDTO  
SDATA  
Figure 16. EXT Slave Mode  
MS0684-E-02  
2008/12  
- 22 -  
 
 复制成功!