[AK4372]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz,19.8MHz, 26MHz
or 27MHz) is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output
frequency is selected between 32fs or 64fs, by BF bit (Table 10).
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4372
DSP or μP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
32fs, 64fs
1fs
LRCK
SDTO
SDATA
Figure 11. PLL Master Mode
PS1
0
0
PS0
0
1
MCKO
256fs
128fs
64fs
(default)
1
0
1
1
32fs
Table 9. MCKO Frequency (PLL mode, MCKO bit = “1”)
BF bit
BICK Frequency
0
1
32fs
64fs
(default)
Table 10. BICK Output Frequency at Master Mode
MS0684-E-02
2008/12
- 19 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
