[AK4372]
Rch
Lch
LRCK
BICK
Don’t
care
Don’t
care
15 14
19 18
0
4
SDATA
16bit
15 14
19 18
0
4
15 14
19 18
Don’t
care
Don’t
care
SDATA
20bit
1
3
0
4
1
0
Don’t
care
Don’t
care
1
0
SDATA
24bit
23 22
1
0
23 22
8
8
3
23 22
4
Figure 19. Mode 2 Timing (LRP = BCKP bits = “0”)
Lch
Rch
LRCK
BICK
Don’t
care
SDATA
16bit
Don’t
15 14
0
4
15 14
19 18
0
4
15
19
care
Don’t
care
SDATA
20bit
Don’t
care
19 18
23 22
1
3
0
4
1
0
Don’t
care
SDATA
24bit
Don’t
care
1
0
1
0
23 22
8
3
8
4
23
BICK
(32fs)
SDATA
16bit
0
15 14
6
5
4
3
2
1
5
4
3
2
1
0
15 14
0
6
15
Figure 20. Mode 3 Timing (LRP = BCKP bits = “0”)
MS0684-E-02
2008/12
- 25 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
