[AK4372]
OPERATION OVERVIEW
■ System Clock
There are the following six clock modes to interface with external devices (Table 1 and Table 2).
Mode
PLL Master Mode
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 4
Figure
Figure 11
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
EXT Master Mode
1
1
1
0
0
0
See Table 4
See Table 4
See Table 4
Figure 12
Figure 13
Figure 14
0
0
1
0
x
x
Figure 15
Figure 16
EXT Slave Mode
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
MCKO pin
L
Selected by
PS1-0 bits
L
MCKI pin
BICK pin
LRCK pin
Output
(Selected by
BF bit)
Selected by
PLL4-0 bits
Output
(1fs)
PLL Master Mode
1
0
1
Input
(32fs ∼ 64fs)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
Selected by
PLL4-0 bits
Input
(1fs)
Selected by
PS1-0 bits
Input
(Selected by
PLL4-0 bits)
Input
(32fs ∼ 64fs)
Output
(Selected by
BF bit)
Input
(32fs ∼ 64fs)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
Input
(1fs)
0
0
0
0
L
L
L
L
GND
GND
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
Input
(1fs)
Selected by
FS3-0 bits
Output
(1fs)
EXT Master Mode
EXT Slave Mode
Selected by
FS3-0 bits
Input
(1fs)
Table 2. Clock pins state in Clock Mode
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4372 is power-down mode (PDN pin = “L”) and exits reset state, the AK4372 is slave mode. After exiting reset state,
the AK4372 changes to master mode by setting M/S bit = “1”.
When the AK4372 is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The LRCK
and BICK pins of the AK4372 should be pulled-down or pulled-up by a resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
1
Slave Mode
Master Mode
(default)
Table 3. Select Master/Slave Mode
MS0684-E-02
2008/12
- 16 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
