[AK4372]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL4-0 and FS3-0 bits (Table 4, Table 5, Table 6). The PLL lock time is shown in Table 4, whenever the AK4372 is
supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Setting of PLL Mode
Mode
PLL4 PLL3 PLL2 PLL1 PLL0
Reference Clock
fs
R,C at VCOC PLL Lock
(Note 31)
Time (typ)
C[F]
R[Ω]
10k
10k
10k
10k
10k
15k
10k
10k
15k
10k
10k
10k
10k
10k
6.8k
6.8k
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MCKI 11.2896MHz
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 2
Type 2
Type 3
Type 4
Table 6
Table 6
Table 6
22n
22n
47n
22n
22n
330n
47n
47n
330n
47n
22n
22n
22n
22n
47n
47n
20ms
20ms
20ms
20ms
20ms
100ms
20ms
20ms
100ms
20ms
20ms
20ms
20ms
20ms
20ms
20ms
80ms
(default)
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
BICK
BICK
LRCK
N/A
14.4MHz
12MHz
19.2MHz
15.36MHz
13MHz
19.68MHz
19.8MHz
26MHz
27MHz
13MHz
26MHz
19.8MHz
27MHz
32fs
9
10
11
12
13
14
15
16
64fs
fs
6.8k 330n
Others Others
Note 31. Refer to Table5 about Type1-4
Note 32 : Clock jitter is lower in Mode10-13 than Mode5/ 7/ 8/ 9 respectively
Note 33. Modes 14~16 are available at Slave Mode only.
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5.
fs
Mode FS3 FS2 FS1 FS0
Type 1
48kHz
24kHz
12kHz
32kHz
16kHz
8kHz
44.1kHz
22.05kHz
11.025kHz
Type 2
Type 3
Type 4
0
1
2
4
5
6
8
9
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
48.0007kHz 47.9992kHz 47.9997kHz
24.0004kHz 23.9996kHz 23.9999kHz
12.0002kHz 11.9998kHz 11.9999kHz
32.0005kHz 31.9994kHz 31.9998kHz
16.0002kHz 15.9997kHz 15.9999kHz
8.0001kHz
7.9999kHz
7.9999kHz
44.0995kHz 44.0995kHz 44.0995kHz (default)
22.0498kHz 22.0498kHz 22.0498kHz
11.0249kHz 11.0249kHz 11.0249kHz
10
3, 7,
11-15
Others
N/A
N/A
N/A
N/A
Table 5. Setting of Sampling Frequency (PLL reference clock input is the MCKI pin) (N/A: Not available)
MS0684-E-02
2008/12
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
