[AK4359A]
■ Audio Serial Interface Format
In parallel control mode, the DIF0 and TDM0 pins as shown in Table 7 can select four serial data modes. The register
value of DIF1-0 and TDM1-0 bits are ignored. In serial control mode, the DIF2-0 and TDM1-0 bits shown in Table 8 can
select 11 serial data modes. Initial value of DIF2-0 bits is “010”. The setting of the DIF1 pin is ignored. In all modes the
serial data is MSB-first, 2’s complement format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20
MSB justified formats by zeroing the unused LSBs.
In parallel control mode, when the TDM0 pin = “L”, the audio interface format is TDM256 mode (Table 7). The audio
data of all DACs (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is ignored. BICK should be
fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is MSB-first, 2’s complement
format. The input data to the SDTI1 pin is latched on the rising edge of BICK.
In serial control mode, when the TDM0 bit = “1” and the TDM1 bit = “0”, the audio interface format is TDM256 mode
(Table 8), and the audio data of all DACs (eight channels) is input to the SDTI1 pin. The input data to the SDTI2-4 pins is
ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is
MSB-first, 2’s complement format. The input data to the SDTI1 pin is latched on the rising edge of BICK. In TDM128
mode (TDM0 bit = “1” and TDM1 bit = “1”, Table 8), the audio data of DACs (four channels; L1, R1, L2, R2) is input to
the SDTI1 pin. The other four data (L3, R3, L4, R4) are input to the SDTI2 pin. The input data to SDTI3-4 pins is ignored.
BICK should be fixed to 128fs. The audio data is MSB-first, 2’s complement format. The input data to SDTI1-2 pins is
latched on the rising edge of BICK.
Mode
Normal
TDM0B DIF0 SDTI Format
LRCK BICK Figure
2
3
5
6
H
H
L
L
L
H
L
24-bit MSB Justified
24-bit I2S Compatible
24-bit MSB Justified
24-bit I2S Compatible
H/L
L/H
↑
Figure 3
Figure 4
≥48fs
≥48fs
256fs Figure 5
256fs Figure 6
TDM256
H
↓
Table 7. Audio Data Formats (Parallel control mode)
Mode
TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format
LRCK BICK Figure
0
1
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
16-bit LSB Justified
20-bit LSB Justified
24-bit MSB Justified
24-bit I2S Compatible
H/L
H/L
H/L
L/H
Figure 1
Figure 2
Figure 3
Figure 4
≥32fs
≥40fs
≥48fs
≥48fs
Normal
4
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
0
24-bit LSB Justified
N/A
H/L
Figure 2
≥48fs
N/A
TDM256
TDM128
5
6
7
24-bit MSB Justified
24-bit I2S Compatible
24-bit LSB Justified
N/A
256fs Figure 5
256fs Figure 6
256fs Figure 7
↑
↓
↑
N/A
8
9
24-bit MSB Justified
24-bit I2S Compatible
24-bit LSB Justified
128fs Figure 8
128fs Figure 9
128fs Figure 10
↑
↓
↑
10
Table 8. Audio Data Formats (Serial control mode) (N/A: Not available)
MS1010-E-01
2008/10
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
