[AK4344]
2.3-wire μP I/F mode (MODE bit = “1”)
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). AK4344 latches the data on the rising edge of CCLK, so data should clocked in
on the falling edge. The writing of data becomes valid by 16th CCLK after a high to low transition of CSN. CSN should
be set to “H” once after 16 CCLKs for each address. The clock speed of CCLK is 5MHz (max).
PDN pin = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers
are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (Fixed to “01”)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 18. Control I/F Timing
*The AK4344 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4344 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
■ DAC input select
The AK4344 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). In 3-wire μP I/F
mode, the AK4344 can select the input data of DAC from SDTI1 or SDTI2 data.
MODE
SEL
DAC input
μP / IF
4-wire
3-wire
3-wire
0
1
1
x
0
1
SDTI1
SDTI1
SDTI2
(x: Don’t care)
Table 5. DAC Input
MS0641-E-00
2007/06
- 18 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
