[AK4344]
SYSTEM DESIGN
Figure 19 and Figure 20 shows the system connection diagram. The evaluation board is available which demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
Master Clock
64fs
MCLK
BICK
SDTI
TEST2
1
2
3
4
5
6
7
8
16
CDTO 15
VDD 14
VSS 13
Analog Supply
2.7 to 3.6V
24bit Audio Data
fs
+
10u
0.1u
4.7u
LRCK
PDN
AK4344
+
Reset & Power down
VCOM 12
CSN
LOUT
ROUT
TEST1
11
10
9
Lch Out
Rch Out
Micro
Controller
CCLK
CDTI
Digital Ground
Analog Ground
Figure 19. Typical Connection Diagram (Mode bit = “0”, 4 wire mode )
24bit Audio Data2
Master Clock
64fs
MCLK
BICK
SDTI
TEST2
1
2
3
4
5
6
7
8
16
SDTI2 15
VDD 14
VSS 13
Analog Supply
2.7 to 3.6V
24bit Audio Data1
fs
+
10u
0.1u
4.7u
LRCK
PDN
AK4344
+
Reset & Power down
VCOM 12
CSN
LOUT
ROUT
TEST1
11
10
9
Lch Out
Rch Out
Micro
Controller
CCLK
CDTI
Digital Ground
Analog Ground
Figure 20. Typical Connection Diagram (Mode bit = “1”, 3 wire mode )
MS0641-E-00
2007/06
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
