[AK4344]
■ μP Control Interface
The AK4344 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”).
1.4-wire μP I/F mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “01”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after 16 CCLKs. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
CDTO
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
WRITE
READ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Hi-Z
CDTO
D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address: (Fixed to “01”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 17. 4-wire Serial Control I/F Timing
*When the AK4344 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
MS0641-E-00
2007/06
- 17 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
