[AK4344]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Control 1
01H Control 2
02H Control 3
1
0
0
0
1
0
0
0
0
0
DIF1
DFS0
INVR
DIF0
DEM1
MODE
PW
DEM0
0
RSTN
GAIN
SEL
DFS1
INVL
Notes:
For addresses from 03H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
The bits shown as “0” should be written “0” and the bits shown as “1” should be written “1”.
■ Register Definitions
Addr Register Name
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
00H Control 1
R/W
DIF1
DIF0
PW
RSTN
R/W
Default
1
0
0
0
1
1
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes the click noise occurs. It can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF1-0: Audio data interface formats (Table 3)
Initial: “11”, Mode 3
MS0641-E-00
2007/06
- 19 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
