[AK4344]
■ Reset Function
(1) Reset by RSTN bit
When RSTN bit =0, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage. Figure 15 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
Digital Block
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(1)
(1)
(3)
(2)
(3)
D/A Out
(Analog)
(4)
Clock In
MCLK,LRCK,BICK
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “0”).
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
Figure 15. Reset Sequence Example1
MS0641-E-00
2007/06
- 15 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
