T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
9 HDLC with FIFO Module (continued)
9.3 HDLC Receiver (continued)
9.3.1 HDLC Receiver Initialization (continued)
Figure 11 represents a sequence of snapshots in time of the receiver FIFO.
In Figure 11 (a), the FIFO is empty, so HRDA = 00h.
In Figure 11 (b), the first five bytes of a packet have been loaded into the FIFO; register HRDA indicates that there
is no status byte in the FIFO (HRDA[SWRF] = 0) and also indicates the number of bytes currently in the FIFO
(HRDA[NBNSW] = 05h).
In Figure 11 (c), a complete packet has been loaded into the FIFO and part of a second packet has been loaded. In
this case, HDRA[SWRF] = 1, which indicates that there is a status byte in the receiver FIFO. HRDA[NBNSW] =
09h indicates that the status byte is the ninth byte in the FIFO.
In Figure 11 (d), the second packet has been completely loaded into the receiver FIFO, part of a third packet has
been received, and some bytes of the first packet have been read by the microcontroller.
Figure 11 (e) represents the case in which the microcontroller has read all bytes of the first packet except its status
byte. A new read of the FIFO (HRX register) will cause the HRDA register to point to the status byte of the second
packet, as shown in Figure 11 (f).
FREE
SPACE
FREE
SPACE
P2-B2
P2-TEI
P2-SAPI
P1-STATUS
P1-B7
P1-B6
P1-B5
P1-B4
P1-B3
UDP #2
UDP #1
FREE
SPACE
(a)
(b)
(c)
P1-B4
P1-B3
P1-B2
P1-TEI
P1-SAPI
P1-B2
P1-TEI
P1-SAPI
UDP #1
HRDA = 00h
HRDA = 05h
HRDA = 89h
FREE
SPACE
FREE
SPACE
FREE
SPACE
UDP #3
P3-SAPI
P2-STATUS
P2-B7
P2-B6
P2-B5
P2-B4
P2-B3
P3-B2
P3-TEI
P3-SAPI
P2-STATUS
P2-B7
P2-B6
P2-B5
P2-B4
P2-B3
P2-B2
UDP #3
P3-B2
P3-TEI
P3-SAPI
P2-STATUS
P2-B7
P2-B6
P2-B5
P2-B4
P2-B3
UDP #3
UDP #2
(d)
(e)
(f)
UDP #2
P2-B2
P2-TEI
P2-SAPI
P1-STATUS
P1-B7
UDP #2
P1-B6
UDP #1
P1-B5
P2-TEI
P2-B2
P1-B4
P1-B3
P2-SAPI
P1-STATUS
P2-TEI
P2-SAPI
HRDA = 89h
HRDA = 86h UDP #1
HRDA = 81h
5-7098F
Figure 11. HDLC Receiver FIFO Snapshot Sequence
Lucent Technologies Inc.
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