T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
6 Functional Modules (continued)
6.13 Serial Port Timing
As per the Intel* 80C32 data book, there are two inputs to the UART module, TXclock and RXclock, which control
the transmission and reception of serial data, respectively. For each of these inputs, it is possible to independently
select either timer 1 or timer 2 as the source. This selection is controlled by the RCLK and TCLK bits in the SFR
register T2CON, which controls the mode of operation of timer 2. The RCLK/TCLK options are shown in Table 18.
Table 18. Standard 80C32 RCLK/TCLK Options
RCLK
TCLK
RXclock
timer 1
timer 1
timer 2
timer 2
TXclock
timer 1
timer 2
timer 1
timer 2
0
0
1
1
0
1
0
1
The UART module in the Lucent 80C32 has only one clock input, which is used to control both reception and trans-
mission. This limitation results in the following truth table (Table 19), which illustrates that both RXclock and
TXclock must be drawn from the same source, either timer 1 or timer 2, depending on the value selected for TCLK.
Table 19. Lucent 80C32 RCLK/TCLK Options
RCLK
TCLK
RXclock
timer 1
timer 2
TXclock
timer 1
timer 2
0
1
0
1
The only cases impacted are cases where the UART transmission and reception functions have to be performed
with different clocks. Completely independent selection of RXclock and TXclock is not possible, as is seen by com-
paring Table 18 and Table 19.
* Intel is a registered trademark of Intel Corporation.
Lucent Technologies Inc.
25
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