T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
Note that P1.1 is not available on the 80C32 block.
Normally, this pin can be used as the T2EX signal for
timer 2 on an 80C32. Since this input is not available
on the NTN, the timer 2 functions that are normally
controlled by the T2EX input are not accessible on the
NTN.
6 Functional Modules (continued)
6.12 Special Instructions for Using the
Lucent 80C32 Block
There are some differences in operation between the
Lucent 80C32 block and a standard 80C32. Attention
must be paid to these differences in order to ensure
trouble-free operation.
Also note that on a standard 80C32, timer 2 has a pro-
grammable clock out mode in which P1.0 is used to
output a square wave whose frequency is controlled by
timer 2. Since P1.0 can only be used as the timer 2
input on the NTN, this mode is not allowed.
6.12.1 Port Configuration
The Lucent Technologies 80C32 I/O ports are con-
trolled by a direction register that determines whether
the port is an input or output. Normal instruction and
data accesses will operate properly without writing to
the direction registers. However, in order to use the
ports as inputs or outputs, the direction registers must
be set accordingly. Writing a 0 to the corresponding bit
of the direction register will configure the pin as an out-
put, and the content of the port latch will be driven onto
the pin. Writing a 1 to the corresponding bit of the direc-
tion register will configure the pin as an input.
6.12.1.3 Port 3
All of the pins on port 3 are used by the NTN device.
The following is a summary of the usage requirements
for the pins of port 3:
■ P3.1, P3.0. The NTN device allows P3.1 and P3.0 to
be used as general-purpose I/O in addition to their
primary purpose of supporting UART connections via
the RXD and TXD functions. In this case, the corre-
sponding bits in the port 3 direction register must be
set according to the use of the pins.
The direction registers reside in an unused area of the
SFR address space of the 80C32 at the addresses
shown in Table 17.
■ P3.3, P3.2. The NTN device uses P3.3 and P3.2 as
general external interrupt sources XINT1 and XINT0.
Therefore, bits 3 and 2 in the port 3 direction register
must be set to 1 to configure these bits as inputs.
6.12.1.1 Ports 0 and 2
■ P3.5, P3.4. The only allowed use for these bits on
the NTN device is as the timer 1 and timer 0 inputs
(when bits GPAF1[GPAF1.6] and GPAF1[GPAF1.5]
are set, respectively). Therefore, bits 5 and 4 in the
port 3 direction register must be set to 1 to configure
these bits as inputs. This is the default state on the
80C32 block.
In the NTN, ports 0 and 2 are dedicated to accessing
memory, and therefore, no action is required with
regard to the setting of the direction control registers.
6.12.1.2 Port 1
Port 1 is not available on the NTN device, with the
exception of P1.0, which is used as the timer 2 input
when bit GPAF1[GPAF1.7] is set. This is the only
allowed use for P1.0 on the NTN device, and therefore,
bit 0 in the port 1 direction register must be set to 1 to
configure this bit as an input. This is the default on the
80C32 block.
■ P3.7, P3.6. The only allowed use for these bits on
the NTN device is as the WR and RD outputs. Since
normal instruction and data accesses will operate
properly without writing to the direction registers, bits
7 and 6 in port 3 direction register are don’t cares.
Table 17. Port Direction Registers
Direction Control Register Port #
SFR Address
0xa4
Default Value
Default State
Input
Port 0
Port 1
Port 2
Port 3
FFh
FFh
00h
FFh
0xa5
Input
0xa6
Output
Input
0xa7
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Lucent Technologies Inc.
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