T9000
Preliminary Data Sheet
November 2000
ISDN Network Termination Node (NTN) Device
4 Pin Information (continued)
Table 5. 80C32 External Access Pins (27)
The 80C32 external access pins change function when the 80C32 block is placed in on-circuit emulation (ONCE)
mode (see Section 6.9, On-Circuit Emulation (ONCE) Mode). The following table lists the normal function for each
pin or group of pins first, followed by the function when in ONCE mode.
Pin Name Pin # Type*
Pin Description
AD[7:0]
11—4
I/O Multiplexed Low-Order Address/Data Bus. Used when accessing external mem-
ory. AD[7:0] are open-drain bidirectional I/O ports requiring external pull-ups.
—
I/O ONCE mode. AD[7:0] are inputs in all cases except during the read phase of an
internal RAM access, where they become outputs to allow the internal RAM to
drive data onto the bus to be read by the emulator.
A[15:8]
20—13
O
Upper Address Bus. Used when accessing external memory. A[15:8] are open-
drain, bidirectional I/O ports requiring external pull-ups. In normal mode, they are
outputs.
—
2
I
ONCE mode. A[15:8] are inputs. If the address is within the range 0K—4K, the chip
will execute the read/write operation on the address indicated. The NTN will not
respond to addresses above 4K.
ALE
O
Address Latch Enable. Output pulse for latching the low byte of the address dur-
ing an access to external memory. In normal operation, ALE is emitted at a con-
stant rate of 1/6 the oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each access to external data
memory.
—
1
I
ONCE mode. ALE is an input that is driven directly by the emulator’s ALE signal
and is used to latch the address applied on A[15:7], AD[7:0].
O
Program Store Enable (Active-Low). Read strobe output to external program
memory. When the 80C32 is executing code from external program memory, PSEN
is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory. PSEN is not activated during
fetches from internal program memory.
PSEN
—
27
—
HZ ONCE mode. PSEN is 3-stated.
O
I
Read Strobe (Active-Low). External data memory read strobe output.
RD
WR
ONCE mode. RD is an input that is driven directly by the emulator’s ALE signal and
used to access internal memory locations from 0K—4K. The NTN will not respond
to addresses above 4K.
28
—
O
I
Write Strobe (Active-Low). External data memory write strobe output.
ONCE mode. WR is an input that is driven directly by the emulator’s ALE signal and
used to access internal memory locations from 0K—4K. The NTN will not respond
to addresses above 4K.
99
I
External Interrupt 0 (Active-Low). Input for driving external interrupt #0 signal on
80C32. This signal is fed to the UCI module where it is combined with the rest of
the type 0 interrupts from the internal NTN circuitry (i.e., those in register GIR0),
and the result is presented to the 80C32 INT0_B input.
XINT0
—
OD ONCE mode. Interrupt source 0 output. Open-drain output. The UCI module drives
this signal low whenever an internal interrupt type 0 condition occurs.
* I = input, O = output, HZ = high-impedance, OD = open-drain output, Id = input with an internal 50 kΩ pull-down, IU = input with an internal
100 kΩ pull-up.
Lucent Technologies Inc.
11
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