Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
4 Electrical Characteristics (continued)
4.10 ac Electrical Characteristics, Microprocessor Timing
4.10.1 Microprocessor Access Intel Multiplexed Write and Read Cycles
For Intel write and read cycles, when RDY is low, wait-states are inserted. RDY is brought high when tIACC is met.
This is true for both read and write cycles.
AD[7:0]
A[1:0]
tAS tAH
D[7:0]
tDS
tDH
ALE
CS
WR
tRDY
tIACC
(RDY DRIVEN LOW DURING
MEMORY ACCESSES ONLY)
RDY
5-6124.bF
Figure 29. Microprocessor Access Intel Multiplexed Write Cycle
AD[7:0]
A[1:0]
tAS tAH
D[7:0]
tDV
tDI
ALE
CS
RD
tRDY
tIACC
(RDY DRIVEN LOW DURING
MEMORY ACCESSES ONLY)
RDY
5-6125.bF
Figure 30. Microprocessor Access Intel Multiplexed Read Cycle
Lucent Technologies Inc.
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AGERE [ AGERE SYSTEMS ]
