Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
4 Electrical Characteristics (continued)
4.10 ac Electrical Characteristics, Microprocessor Timing (continued)
4.10.3 Microprocessor Access Intel Demultiplexed Write and Read Cycles
A[1:0]
tAS
tAH
CS
WR
tIACC
tRDY
(RDY DRIVEN LOW
DURING MEMORY
ACCESSES ONLY)
RDY
tDS
tDH
D[7:0]
5-6128.cF
Figure 33. Microprocessor Access Intel Demultiplexed Write Cycle
A[1:0]
tAS
tAH
CS
RD
tIACC
tRDY
(RDY DRIVEN LOW
DURING MEMORY
ACCESSES ONLY)
RDY
tDV
tDI
D[7:0]
5-6128.bF
Figure 34. Microprocessor Access Intel Demultiplexed Read Cycle
Table 81. Microprocessor Access Timing
(See Figures 29 through 34.)
Symbol
Description
Condition
Min
Max
Unit
tAS
tAH
Address Setup Time
Address Hold Time
Data Valid
Load = 100 pF
7
0
—
—
ns
ns
ns
ns
ns
ns
ns
—
tDV
—
—
0
13
tDI
Data Invalid
—
11
tRDY
tIACC
Active to Ready Low (Intel)
Active to Ready High (Intel)
Memory Access
Memory Access
—
145
14
255
Register Access
Memory Access
—
130
14
255
tMACC
Active to DTACK Low (Motorola)
tDS
tDH
Data Setup Time
Data Hold Time
—
—
8
0
—
—
ns
ns
Lucent Technologies Inc.
93
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