Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
Table of Contents (continued)
Page Tables
Tables
Page
Table 43. HSL: H-Bus Stream Control, Low Byte,
Table 63. DIAG1: Diagnostics Register 1, 0x30..........67
Table 64. DIAG2: Diagnostics Register 2, 0x31..........68
Table 65. DIAG3: Diagnostics Register 3, 0x32..........68
Table 66. Device Identification Register, 0xFE ...........70
Table 67. GMODE: Global Mode Register, 0xFF.......70
Table 68. LPUE Control Pins ......................................71
Table 69. Time-Slot Bit Decoding ..............................73
Table 70. IDR: Indirect Data Register, Local
0x10............................................................37
Table 44. HSL: H-Bus Stream Control, High Byte,
0x11............................................................38
Table 45. Permitted Tag Extensions ..........................40
Table 46. CKM: Clocks, Main Clock Selection,
0x00 ...........................................................49
Table 47. CKN: Clocks, NETREF Selections,
0x01 ...........................................................50
Table 48. CKP: Clocks, Programmable Outputs,
0x02 ...........................................................51
Table 49. CKR: Clocks, Resource Selection,
0x03 ...........................................................52
Table 50. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ..........................................53
Table 51. CK32 and CK10: Clocks, Locals 3, 2, 1,
and 0, 0x05 and 0x06 ................................55
Table 52. CON Register 0x0E ....................................56
Table 53. LREF Pairs..................................................57
Table 54. CKM (0x00) CKSEL Values to Select
LREF Pairs .................................................57
Table 55. FRHA, Frame Group A High Address
and Control, 0x21 .....................................59
Table 56. FRHB, Frame Group B High Address
and Control, 0x23 ......................................59
Table 57. FRPH: Frame Group B, Programmed
Output, High, 0x25 ....................................61
Table 58. CLKERR1 and CLKERR2: Error Indicator
and Current Status, 0x28 and 0x29 ...........62
Table 59. CLKERR3: Error Indicator and Current
Status, 0x2C .............................................63
Table 60. SYSERR: System Error Register,
Connections Only ......................................74
Table 71. IDR: Indirect Data Register, H-Bus
Connections Only .....................................75
Table 72. Crystal Specifications .................................83
Table 73. Use of an Oscillator as an Alternative to
Using a Crystal ..........................................83
Table 74. Electrical Drive Specifications—CT_C8
and /CT_FRAME .......................................84
Table 75. dc Electrical Characteristics, All
Other Pins ..................................................84
Table 76. ac Electrical Characteristics, Timing,
H-Bus (H.100 Spec., Rev. 1.0) .................87
Table 77. ac Electrical Characteristics, Skew
Timing, H-Bus (H.100 Spec., Rev. 1.0) ....88
Table 78. Reset and Power On ..................................89
Table 79. ac Electrical Characteristics, Local
Streams, and Frames ................................89
Table 80. L_SC[3:0] and Frame Group Rise and
Fall Time.....................................................89
Table 81. Microprocessor Access Timing ..................93
Table 82. Clock Register Programming Profile for
the Four Previous Examples ...................102
Table 83. Table of Special Cases (Exceptions) .......105
0x2A ..........................................................63
Table 61. JTAG Instruction Set .................................64
Table 62. JTAG Scan Register .................................65
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