Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
1 Product Overview (continued)
1.3 Pin Information (continued)
Table 1. Pin Descriptions: Clocking and Framing Pins
Symbol
L_REF[7:0]
Pin
Ball
Type
I
Name/Description
Local Frame Reference Inputs. 50 kΩ internal pull-up.
45—38 P3, N4, R1, P2, N3, M4,
P1, N2
/C16+
/C16–
102
101
R14
P13
I/O H-MVIP 16.384 MHz Clock Signals. Differential 24 mA drive,
Schmitt in, 50 kΩ internal pull-up.
/C4
104
U16
I/O MVIP 4.096 MHz Clock. 8 mA drive, Schmitt in, 50 kΩ internal
pull-up.
C2
106
T17
I/O MVIP 2.048 MHz Clock. 8 mA drive, Schmitt in, 50 kΩ internal
pull-up.
SCLK
110
R17
I/O SC-Bus 2/4/8 MHz Clock. 24 mA drive, Schmitt in, 50 kΩ internal
pull-up.
108
P15
I/O SC-Bus Inverted 4/8 MHz Clock (Active-Low). 24 mA drive,
Schmitt in, 50 kΩ internal pull-up.
SCLKX2
L_SC[3:0]
36—33
M3, N1, M2, M1
O
Local Selected Clocks. 1.024 MHz, 2.048 MHz, 4.096 MHz,
8.192 MHz, 16.384 MHz, frame (8 kHz), or secondary (NETREF).
8 mA drive, 3-state.
FGA[5:0]
FGA[11:6]
FGB[5:0]
94—99
87—92
R12, T13, U14, P12,
R13, T14
O
Frame Group A. 8 mA drive, 3-state.
T11, P11, R11, U12,
T12, U13
80—85 U9, R9, U10, T10, R10,
U11
O
Frame Group B. 8 mA drive, 3-state.
FGB[11:6]
PRIREFOUT
PLL1VDD
73—78 U6, T7, R8, U7, T8, U8
58
53
P5
U1
O
Output from Primary Clock Selector/Divider. 8 mA drive.
—
PLL #1 VCO Power. This pin must be connected to power, even if
PLL #1 is not used.
PLL1GND
51
No ball for this
signal, internally
connected.
—
PLL #1 VCO Ground. This pin must be connected to ground,
even if PLL #1 is not used.
EN1
55
54
T3
U2
A2
I
PLL #1 Enable. Requires cap to VSS to form power-on reset, or
may be driven with RESET line. 50 kΩ internal pull-up.
4MHZIN
PLL2VDD
PLL2GND
I
PLL #1 Rate Multiplier. Can be 2.048 MHz or 4.096 MHz.
50 kΩ internal pull-up.
208
206
—
—
PLL #2 VCO Power. This pin must be connected to power, even if
PLL #2 is not used.
No ball for this
signal, internally
connected.
PLL #2 VCO Ground. This pin must be connected to ground,
even if PLL #2 is not used.
EN2
3
C2
I
PLL #2 Enable. Requires cap to VSS to form power-on reset, or
may be driven with RESET line. 50 kΩ internal pull-up.
3MHZIN
XTALIN
1
47
A1
R2
T1
C4
E1
I
PLL #2 Rate Multiplier. Input, 50 kΩ internal pull-up.
16.384 MHz Crystal Connection or External Clock Input.
16.384 MHz Crystal, Feedback Connection.
I
XTALOUT
TCLKOUT
CLKERR
48
O
O
O
203
13
Selected output to drive framers. 8 mA drive, 3-state.
Clock Error. Logical OR of CLKERR register flags (only). 8 mA
drive, 3-state.
SYSERR
12
F3
O
System Error. Logical OR of all CLKERR and SYSERR register
flags. 8 mA drive, 3-state.
8
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