Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
Table of Contents (continued)
Page Tables
Figures
Page
Figure 35. E1, CT Bus Master, Compatibility
Table 16. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ........................................ 18
Table 17. CK32: Clocks, Locals 3 and 2, 0x05 ........ 18
Table 18. CK10: Clocks, Locals 1 and 0, 0x06 ........ 18
Table 19. CKMD: Clocks, Main Divider; CKND:
Clocks, NETREF Divider; CKRD: Clocks,
Clock Master, Clock Source = 2.048 MHz
from Trunk................................................98
Figure 36. T1, CT Bus Master, Compatibility
Clock Master, Clock Source = 1.544 MHz
from Trunk................................................99
Figure 37. E1, Slave to CT Bus, Clock Source
Is Either a 16 MHz or a 4 MHz or a 2 MHz
and Frame, NETREF Source = 2.048 MHz
from Trunk..............................................100
Figure 38. T1, Slave to CT Bus, Clock Source
Is Either a 16 MHz or a 4 MHz or a 2 MHz
and Frame, NETREF Source = 1.544 MHz
from Trunk..............................................101
Figure 39. Constant Delay Connections,
CON[1:0] = 0X........................................104
Figure 40. Minimum Delay Connections,
CON[1:0] = 0X........................................105
Figure 41. Mixed Minimum/Constant Delay
Connections, CON[1:0 = 10] ..................106
Figure 42. Extended Linear (Mixed Minimum/Constant)
Delay, CON[1:0] = 11 .............................107
Resource Divider, 0x07, 0x08, 0x09 ........ 19
Table 20. LBS: Local Stream Control, 0x0C ............ 19
Table 21. CON: Connection Delay Type, 0x0E ........ 19
Table 22. HSL: H-Bus Stream Control, Low Byte,
0x10 ......................................................... 19
Table 23. HSH: H-Bus Stream Control, High Byte,
0x11 ......................................................... 19
Table 24. GPD, General-Purpose Direction Control
Register, 0x17............................................ 19
Table 25. GPR: General-Purpose I/O Register,
0x18 ......................................................... 20
Table 26. FRLA: Frame Group A, Start Address
Low, 0x20 ................................................. 20
Table 27. FRHA: Frame Group A, High Address and
Control, 0x21 ............................................ 20
Table 28. FRLB: Frame Group B, Start Address
Low, 0x22 ................................................. 20
Table 29. FRHB: Frame Group B, High Address
and Control, 0x23 ..................................... 20
Table 30. FRPL: Frame Group B, Programmed
Output, Low, 0x24 .................................... 21
Table 31. FRPH: Frame Group B, Programmed
Output, High, 0x25 ................................... 21
Table 32. CLKERR1: Clock Error Register, Error
Indicator, 0x28 ......................................... 21
Table 33. CLKERR2: Clock Error Register, Current
Status, 0x29 ............................................. 21
Table 34. SYSERR: System Error Register,
0x2A ......................................................... 21
Table 35. CKW: Clock Error/Watchdog Masking
Register, 0x2B ......................................... 21
Table 36. CLKERR3: Clock Error Register, Current
Status, 0x2C............................................... 21
Table 37. DIAG1: Diagnostics Register 1, 0x30 ....... 22
Table 38. DIAG2: Diagnostics Register 2, 0x31 ....... 22
Table 39. DIAG3: Diagnostics Register 3, 0x32 ....... 22
Table 40. DEV_ID: Device Identification Register,
0xFE .......................................................... 22
Table 41. GMODE: Global Mode Register, 0xFF...... 22
Table 42. LBS: Local Stream Control, 0x0C ............ 28
Tables
Page
Table 1. Pin Descriptions: Clocking and Framing
Pins ...............................................................8
Table 2. Pin Descriptions: Local Streams Pins ............9
Table 3. Pin Descriptions: H-Bus Pins .........................9
Table 4. Pin Descriptions: Microprocessor Interface
Pins .............................................................10
Table 5. Pin Descriptions: JTAG Pins .......................10
Table 6. Pin Descriptions: Power Pins ......................11
Table 7. Pin Descriptions: Other Pins .......................11
Table 8. Addresses of Programming Registers ..........15
Table 9. Master Control and Status Register ............15
Table 10. Address Mode Register ..............................16
Table 11. Control Register Memory Space ................17
Table 12. CKM: Clocks, Main Clock Selection,
0x00 ..........................................................18
Table 13. CKN: Clocks, NETREF Selections,
0x01 ..........................................................18
Table 14. CKP: Clocks, Programmable Outputs,
0x02 ..........................................................18
Table 15. CKR: Clocks, Resource Selection,
0x03 ..........................................................18
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