Ambassador T8100A, T8102, and T8105
H.100/H.110 Interfaces and Time-Slot Interchangers
Advance Data Sheet
November 1999
2 Architecture and Functional Description (continued)
2.5 Clocking Section (continued)
TODJAT/GP6 FROMDJAT/GP7
CT_NETREF1
CT_NETREF2
GP6
EN_NETREF2
GP7
NETREF
CT_NETREF2
EN_NETREF1
NET-
REF
SEL.
DIVIDE-BY-N
DJAT BYPASS
(AND GP6/7 ENABLE)
DIVIDE REGISTER
NETREF
INT/EXT
SELECT
CT_NETREF1
EN_A
C8
CT_C8_A
÷ BY 8
FRAME
/CT_FRAME_A
CT_NETREF1
CT_NETREF2
THESE INPUTS
FORM
TRANSCEIVERS
WITH THE
EN_B
C8
NETREF
SELECT
CT_C8_B
CORRESPONDING
OUTPUTS
FRAME
/CT_FRAME_B
BIT SLIDER
CONTROLS
COMPATIBILITY
CLOCKS DIRECTION
BIT SLIDER
/CT_FRAME_A
FRAME
SEL.
/CT_FRAME_B
/FR_COMP
FRAME SYNC
16.384 MHz
/CT16 ±
4 MHz
INTERNAL CONTROL
CLOCKS AND SYNC
STATE
MACHINES
2.048 MHz
C2
2 MHz
DPLL
4.096 MHz
/C4
CON[5]
PLL #1
BYPASS
CLOCK
SEL.
CT_NETREF1
2.048 MHz
RESOURCE
DIVIDE-BY-N
4.096 MHz
SCLK
65.536 MHz
L_REF0
L_REF7
8.192 MHz
CT_NETREF2
DIVIDE REGISTER
PLL #1
x16
SCSEL
4.096 MHz
SCLKX2
MEMORY
CLOCK
x32
8.192 MHz
CLOCK
CLOCK
SEL.
MAIN
RESOURCE
RATE SELECT
SELECT
CT_NETREF
DIVIDE-BY-N
FRAME
AND
/FR_COMP
CT_C8_A
DIVIDE REGISTER
INPUT
STATE
MACH.
SEC8K
FRAME
CT_C8_B
/C16±
/C4
PLL #2 BYPASS
C2
2.048 MHz
SCLK
SCLKX2
DIVIDE-
BY-2
PLL #2
4.096 MHz
L_SC0
8.192 MHz
THESE INPUTS
FORM
TRANSCEIVERS
WITH THE
CORRESPONDING
OUTPUTS
x 8
x16
16.384 MHz
RATE SELECT
PLL#2 ÷ 2
(FALLBACK PATH*)
DIVIDE-
BY-4
XTALIN
L_SC CTL
(1 OF 4
TCLKOUT
SELECT
L_SC[1:3]
NOT SHOWN)
PRIREFOUT
4MHzIN
3MHzIN
TCLKOUT
ENABLE
TCLKOUT
5-6111dF
* The path for XTALIN divide-by-4 is for fallback only.
Figure 16. Clocking Section
44
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
